Embodiments of the present disclosure relate to methods of manufacturing a semiconductor device and, more particularly, to methods of manufacturing a semiconductor device having a node array.
As semiconductor devices such as dynamic random access memory (DRAM) devices become more highly integrated and more shrunk, DRAM technologies have been continuously developed to realize a minimum feature size of about 20 nanometers or less. However, if the DRAM devices are scaled down, some elements such as storage nodes constituting memory cells of the DRAM devices may also be shrunk to reduce surface areas thereof. In such a case, cell capacitance of the DRAM cells may decrease to degrade cell characteristics, for example, a soft error rate (SER) characteristic. Thus, efforts to increase the cell capacitance of the DRAM devices in a limited area have been continuously required to realize high performance DRAM devices.
A unit memory cell of the DRAM devices may be configured to include a single cell capacitor and a single cell transistor. If the DRAM devices are scaled down, the cell capacitance of the DRAM cells may decrease to reduce a sensing margin of the DRAM cells. Thus, efforts to increase the cell capacitance of the DRAM devices have been continuously required together with shrink of the DRAM devices. In order to increase the cell capacitance of the DRAM cells in a limited area, a height of storage nodes constituting the DRAM cell capacitors may be increased. However, there may be limitations in increasing the height of the storage nodes using only process techniques.
The storage nodes may be formed by etching a mold layer to form through holes (e.g., storage node holes) penetrating the mold layer and by filling the through holes with a conductive material. Thus, a thickness of the mold layer should be increased to increase the height of the storage nodes. However, if the thickness of the mold layer increases, the burden on an etching process for forming the through holes may be increased. Accordingly, an etching margin of the etching process may be reduced and a contact margin between the storage nodes and the underlying cell transistors may also be reduced. That is, if the thickness of the mold layer increases, the through holes may not be fully opened. Further, when the mold layer is removed to expose sidewalls of the storage nodes, the storage nodes may easily lean or fall down. Therefore, it may be difficult to increase the height of the storage nodes. Thus, novel technologies are still required to increase surface areas of the storage modes without degradation of the integration density of the DRAM devices.